1. Field of the Invention
The present invention relates to a memory device, and more particularly to a nonvolatile memory device including a memory cell having a characteristic in that a pass current at the time of data reading is changed in response to a level of binary storage data.
2. Description of the Background Art
In recent years, attention has been focussed on an MRAM Magnetic Random Access Memory) device as a non-volatile memory device in a new generation. An MRAM device is a non-volatile memory device in which non-volatile data storage is performed using a plurality of thin m magnetic elements formed in a semiconductor integrated circuit and a random access is enabled to each of the thin film magnetic elements. Especially, a thin film magnetic elements including a magnetic tunnel junction (MTJ) has been used as a memory cell in recent years and thereby a drastic progress in performance of an MRAM device has been achieved, which is disclosed in the following literature.
(Literature 1)
“A 10 ns Read and Write Non-Volatile Memory Array Using a Magnetic Tunnel Junction and FET Switch in each Cell” (USA), Roy Scheuerlein and 6 others, 2000 IEEE ISSCC Digest of Technical Papers TA 7.2.
Since a memory cell having a magnetic tunnel junction therein (hereinafter, also referred to as an “MTJ memory cell”) can be constructed of one MTJ element and one access element (e.g., a transistor), the memory cell is also advantageous in high integration. An MTJ element has a magnetic layer capable of being magnetized along a direction corresponding to an applied magnetic field, and an MTJ memory cell performs data storage using a characteristic in that an electric resistance (a junction resistance) in the MTJ element alters depending on a magnetic direction of the magnetic layer. Whether or not a magnetic direction of the magnetic layer alters is determined by a strength of the synthetic magnetic field of two magnetic fields generated by data write currents flowing in a write digit line and a bit line, respectively. Hereinafter, a write digit line and a bit line are also collectively referred to as a write current line, and data write currents are also simply referred to as a write current.
A necessity arises for detection of a difference in electric resistance corresponding to a level of storage data in order to read the storage data in an MTJ memory cell. To be concrete, data reading is performed based on a pass current through an MTJ memory cell altering depending on an electric resistance (i.e., storage data).
In general, since data writing is performed according to supply of a write current in an MRAM device, a supply amount of the write current is necessary to be precisely adjusted. Therefore, the following problems have been arisen in data write operation on an MTJ memory cell.
(1) A path length of wiring to a MTJ memory cell from a current source supplying a current for writing data to the selected MTJ memory cell is different according to a location of the MTJ memory cell (hereinafter, also referred to as a selected memory cell). Therefore, wiring resistance from the current source to the selected memory cell is different according to the location of the selected memory cell. Therefore, a write current fluctuates in value, which leads to a loss of a margin of data writing, thereby resulting in a possibility to produce a phenomenon to disable data to be normally written to the selected memory cell.
(2) A current wire connected to a plurality of write current lines provided correspondingly to each of the predetermined units of a plurality of MTJ memory cells is generally longer than a write current line. Therefore, a large parasitic capacitance is generated on the current wire.
A necessity exists for causing a comparatively large current to flow in a selected write current line (in mA units) in writing data to an MTJ memory cell. Hence, a possibility arises that a current generated by the parasitic capacitance is superimposed on a write current for writing data to the MTJ memory cell, essentially in need. Accordingly, an excessively large current generates in the write current line, leading to erroneous data writing to a non-selected memory cell arranged in the vicinity of a selected write current line.
(3) Since a necessity arises for causing much of a current to flow in a write current line when data is written, a voltage applied to a current source for supplying the current to the write current line is set higher than a voltage applied to other circuits. Therefore, an address decode circuit and related circuits thereof included the other circuits and a current source are applied with respective different power supply voltages from each other. As a result, when power is turned on, the current source has a fear to be activated at a timing earlier than the address decode and related circuits thereof. Therefore, if the address decode circuit and related circuits thereof remain in an inactive state when power is turned on, that is, when the current source is activated before the address decode circuit and related circuits thereof are not normally operated, an unnecessary current flows in a write current line, leading to a problem that erroneous data writing is performed to an MTJ memory cell.